Semiconductor fabrication frequently involves formation of conductive materials within openings, trenches or vias to form conductive interconnects. An exemplary prior art process for forming a conductive interconnect is described with reference to FIGS. 1 and 2.
Referring initially to FIG. 1, a semiconductor construction 10 is shown to comprise a semiconductor base 12 supporting an electrically conductive node 14 and an electrically insulative material 16. Base 12 can comprise, for example, a monocrystalline silicon wafer. Although base 12 is shown having a homogeneous composition, it is to be understood that base 12 can comprise numerous layers and integrated circuit devices (not shown). The combination of base 12 with structures 14 and 16, can be referred to as a semiconductor substrate. To aid in interpretation of the claims that follow, the terms “semiconductive substrate” and “semiconductor substrate” are defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
Electrically conductive node 14 can comprise any suitable material or combination of materials, and can, for example, comprise, consist essentially of, or consist of one or both of copper and tungsten.
Electrically insulative material 16 can comprise any of numerous materials, and in some aspects will comprise, consist essentially of one or both of silicon dioxide and silicon nitride. If material 16 comprises silicon dioxide, such can be in either a substantially undoped form, or it can be in a doped form, such as, for example, borophosphosilicate glass (BPSG). Although material 16 is shown as a homogeneous material, it is to be understood that material 16 can comprise a plurality of layers of differing electrically insulative compositions.
An opening 18 extends through material 16 to an upper surface 15 of node 14. The opening 18 has a periphery comprising exposed sidewall surfaces 17 of electrically insulative material 16, and the exposed upper surface 15 of node 14. Opening 18 can have any of numerous shapes, and in some aspects can be a via or trench.
Referring next to FIG. 2, opening 18 is filled with conductive material by first forming a thin adhesive liner 20 within the opening, and subsequently forming a bulk conductive material 22 within the opening to fill the opening. The liner 20 can comprise a metal nitride (such as, for example, titanium nitride), and the bulk material can comprise a metal (such as, for example, tungsten). The liner 20 and bulk conductive material 22 can be formed by, for example, one or both of atomic layer deposition and chemical vapor deposition. In subsequent processing (not shown) the liner material 20 and bulk conductive material 22 can be removed from over insulative material 16 by, for example, chemical-mechanical polishing, while leaving the liner and conductive material within opening 18. The liner and conductive material remaining within the opening 18 can subsequently be utilized as a conductive interconnect for electrically connecting circuitry (not shown) to node 14.
A difficulty encountered in forming the liner 20 and conductive material 22 within opening 18 is that the deposited materials can pinch off a top of opening 18 during formation of the materials within the opening, and such can cause the opening to be less than uniformly filled with the conductive materials. This can decrease operability of an interconnect ultimately formed in the opening, and in particularly problematic cases can destroy operability of an interconnect. A continuing goal of semiconductor processing is to increase packing density across a surface of a semiconductor wafer, and accordingly to reduce the widths (i.e. increase the critical dimensions) of openings associated with semiconductor constructions. Difficulties associated with deposition of conductive materials within openings are exacerbated as the openings increase in critical dimension. Accordingly, there has been a continuing effort to develop new methods for forming conductive materials within openings.
One of the methods being developed for forming conductive materials within openings is to electroless plate the materials into the openings in a manner such that the conductive materials grow upwardly from a surface of a conductive node at the bottom of the openings. The upward growth of the electroless-plated materials can alleviate, and preferably prevent, the above-discussed problem of the materials pinching off the top of an opening before the materials have completely filled the bottom of the opening.
It has proven to be difficult, however, to develop methods which selectively electroplate conductive materials on conductive surfaces relative to insulative surfaces. If the plated materials grow on insulative surfaces (such as, for example, the surfaces 17 of FIG. 1), the plated materials can pinch off the top of an opening before the materials have filled the opening. Ideally, the plated materials would selectively grow on the conductive surface of an electrically conductive node (such as, for example, the surface 15 of node 14 in FIG. 1), and then continue to selectively grow on conductive surfaces relative to insulative surfaces so that the plated material fills the opening by upward growth from conductive surfaces rather than by lateral or sideward growth from insulative surfaces.
For purposes of interpreting this disclosure and the claims that follow, a deposition process is considered to be “selective” for a first surface relative to a second surface if deposition occurs more rapidly in the first surface than the second surface, which can include, but is not limited to, conditions in which the deposition occurs only on the first surface and not on the second surface (i.e., conditions in which the deposition is 100% selective for the first surface relative to the second surface).
A conductive material which is commonly utilized in electroplating processes is nickel. However, a problem in utilizing nickel to fill openings (such as the opening 18 of FIG. 1) is that it can be difficult to electroless plate the nickel on a conductive surface of copper or tungsten (such as the surface 15 of node 14) without first activating such conductive surface. The activation frequently comprises provision of palladium onto the surface to provide loci for subsequent deposition of nickel during an electroless plating process. Unfortunately, the activation conditions can also form loci on the exposed surfaces 17 of insulative material 16, and accordingly can result in electroless plating of nickel along the lateral surfaces 17 of opening 18. The plating of nickel on the lateral surfaces 17 can lead to lateral growth of the electroless-plated nickel across the opening, which can pinch off the opening before the electroless-plated conductive material has entirely filled the opening.
It is desired to develop new methods for electroless-plating of materials within openings which alleviate, and preferably prevent, the various problems discussed above. It is further desired to develop methods for electroless plating which are selective for plating on conductive surfaces relative to insulative surfaces, and which preferably can be conducted without activation of the conductive surfaces.